The present invention relates to a semiconductor device including a semiconductor memory device, and, more particularly, to an internal supply voltage generating circuit of a semiconductor device for dropping an external supply voltage and generating an internal supply voltage provided to an internal circuit, as well as a method for controlling the same.
For decreasing the amount of current consumed, a semiconductor memory device is provided with two internal supply voltage generating circuits to generate internal supply voltages provided to internal circuits. A first internal supply voltage generating circuit (a large power voltage-drop circuit) consumes a relatively large current and supplies a relatively large driving power. A second internal supply voltage generating circuit (a small power voltage-drop circuit) consumes a relatively small current and supplies a relatively small driving power. In an active mode of the semiconductor memory device, the first and second internal supply voltage generating circuits operate and provide internal supply voltages to internal circuits. In a stand-by mode or a power-down mode, the first internal supply voltage generating circuit stops operating, and only the second internal supply voltage generating circuit provides an internal supply voltage to internal circuits. Since only the second internal supply voltage generating circuit operates, the power consumption of the semiconductor memory device is reduced.
In an active mode, the semiconductor memory device may assume a hold state in accordance with a command (active command) from an MPU (microprocessor unit) or a memory controller. For example, if a read command or a write command is not supplied during the period from when a word line is activated by an active command and a sense amplifier begins to operate to when the semiconductor memory device begins to perform a reset (precharge) operation, the semiconductor memory enters a state of an active pause. During the active pause period, power consumption is small because internal circuits include CMOS transistors, which have low power consumption.
However, during the active pause period, a large amount of current flows through the first voltage-drop regulator of the large power voltage-drop circuit, and it is desired to decrease the power consumption therein. For example, Japanese Patent Laid Open No. 7-105682 discloses a semiconductor memory device provided with a first regulator that in an active mode supplies a relatively large driving power to a sense amplifier during operation of the sense amplifier and a second regulator that, after operation of the sense amplifier, supplies a driving power smaller than that of the first regulator. Thus, in write and read operations after operation of the sense amplifier, a minimum required power is supplied, thereby decreasing the power consumption.
More particularly, the semiconductor memory device is provided with three voltage-drop regulators. In a stand-by mode, only one voltage-drop regulator is activated, while in an active mode all three voltage-drop regulators are activated, and the sense amplifier is made to rise rapidly. When the sense amplifier is stable after the lapse of a predetermined time, the semiconductor memory device enters a state of active pause, and the two voltage-drop regulators are inactivated and on stand-by for the next command operation.
However, since two voltage-drop regulators are still activated in an active pause, it is difficult to minimize power consumption of the internal supply voltage generating circuit. The provision of the three voltage-drop regulators also increases the circuit area and results in a more complicated control system.
FIG. 1 is a schematic block diagram of a conventional control circuit 100 for an internal supply voltage generating circuit and a row system circuit. In a memory cell area, a row system circuit 41 is provided for activating a word line and a row decoder, and an internal supply voltage is provided to the row system circuit 41 from a large power voltage-drop regulator 42. The control circuit 100 includes a command detecting circuit 43, a row control circuit 44, a regulator control circuit 50, which acts as an activating signal generating circuit and controls the large power voltage-drop regulator 42, and an active time-out circuit 80.
The command detecting circuit 43 receives an external command, such as chip select signal, row address strobe signal, column address strobe signal, and write enable signal, from external devices (not shown) and detects various commands in accordance with combinations of the signals.
Upon detection of a refresh command, the command detecting circuit 43 provides a row command signal rowz having a high level to the row control circuit 44 and provides a refresh command signal refz having a high level to the active time-out circuit 80.
In response to the row command signal rowz having a high level, the row control circuit 44 produces a row control signal brasz having a high level and subsequently produces a word line activating signal plez having a high level as a memory cell area activating signal, slightly behind the row control signal brasz.
In accordance with the row control signal brasz at high level, the regulator control circuit 50 produces an activating signal enz at high level to activate the large power voltage-drop regulator 42. In response to the word line activating signal plez at high level, the regulator control circuit 50 causes the activating signal enz to fall when the semiconductor device enters an active pause state upon lapse of time t1 after the rise of the activating signal enz.
The row system circuit 41 is activated by the row control signal brasz at high level provided from the row control circuit 44. At this time, a relatively large driving power is provided to the row system circuit 41 from the activated large power voltage-drop regulator 42, so that the row system circuit operates at a high speed. When the row system circuit 41 is stable, the large power voltage-drop regulator 42 is inactivated, and a driving power is provided to the row system circuit 41 from a small power regulator (not shown).
When the refresh command signal refz at high level is supplied from the command detecting circuit 43, the active time-out circuit 80 provides an active time-out signal tout at low level to the row control circuit 44 upon lapse of a predetermined time t2 after the supply of the word line activating signal plez at high level from the row control circuit 44.
In response to the active time-out signal tout at low level, the row control circuit 44 causes the row control signal brasz to fall, thereby inactivating the row system circuit 41. The row control circuit 44 causes the row control signal brasz and the word line activating signal plez to fall, and in response to the activating signal plez, the active time-out circuit 80 causes the active time-out signal tout to rise. Thus, the row control circuit 44 is ready for the next refresh operation.
As shown in FIG. 2, the regulator control circuit 50 includes a detector circuit 51 and a delay circuit 52. The detector circuit 51 is an exclusive OR circuit including three NAND circuits 53, 54, 55 and three inverter circuits 56, 57, 58. When the row control signal brasz and the word line activating signal plez have different levels from each other, the detector circuit 51 provides a detection signal eor at low level to the delay circuit 52. The first NAND circuit 53 receives the word line activating signal plez and the row control signal brasz, which has been inverted by the first inverter circuit 56. The second NAND circuit 54 receives the row control signal brasz and the word line activating signal plez, which has been inverted by the second inverter circuit 57. The third NAND circuit 55 receives output signals from the first and second NAND circuits 53, 54. An output terminal of the third NAND circuit 55 is connected to the delay circuit 52 via the third inverter circuit 58.
The delay circuit 52 is provided with an input circuit, which includes two inverter circuits 69a, 69b and two capacitors 69c, 69d, and an output circuit, which includes a NAND circuit 70a and two inverter circuits 70b, 70c. Between the input circuit and the output circuit are connected a plurality of delay circuits 71. Each delay circuit 71 includes a NAND circuit 71a, an inverter circuit 71b, and a capacitor 71c. 
The detection signal eor of the detector circuit 51 is supplied to the NAND circuit 71a of the first delay circuit 71 via the input circuit and is delayed by the delay time t1, which is determined according to the number of delay circuits 71, and a delay output signal s1 is output from the last delay circuit 71.
The NAND circuit 70a receives the delay output signal s1 from the last delay circuit 71 and the detection signal eor of the detector circuit 51 and provides a NAND output signal as the activating signal enz to the large power voltage-drop regulator 42 via the two inverter circuits 70b and 70c. 
As shown in FIG. 3, if the row control signal brasz rises high during a low-level state of the word line activating signal plez, the detection signal eor falls low. In response to the fall of the detection signal eor, the activating signal enz goes high, whereby the large power voltage-drop regulator 42 is activated, and a relatively large driving power is provided to the row system circuit 41 from the voltage-drop regulator 42.
Then, when the word line activating signal plez rises, the detection signal eor falls, and the activating signal enz falls after a delay time t1 from the rise of the activating signal enz, whereby the large power voltage-drop regulator 42 is inactivated. Thus, when the semiconductor memory device enters an active pause state upon lapse of a predetermined time (delay time t1) after the start of the activating operation, the regulator control circuit 50 inactivates the large power voltage-drop regulator 42.
As shown in FIG. 4, the active time-out circuit 80 includes a detector circuit 81 and a delay circuit 82. The detector circuit 81 includes a NAND circuit 81a, which receives the word line activating signal plez and the refresh command signal refz, and an inverter circuit 81b. When the refresh command signal refz and the word line activating signal plez are at high level, the detector circuit 81 provides a detection signal nol at low level to the delay circuit 82.
The delay circuit 82 is provided with an input circuit, which includes two inverter circuits 83a, 83b and two capacitors 83c, 83d, and an output circuit, which includes a NAND circuit 84a and two inverter circuits 84b and 84c. Between the input circuit and the output circuit are connected a plurality of delay circuits 85. Each delay circuit 85 includes a NAND circuit 85a, an inverter circuit 85b and a capacitor 85c. The active time-out circuit 80 includes a larger number of delay circuits 85 than the delay circuits 71 of the regulator control circuit 50.
When the level of the detection signal nol goes high, an output signal s2 of the final delay circuit 85 rises high after the lapse of delay time t2, which is determined according to the number of delay circuits 85. When the level of the detection signal nol goes low, the output signal s2 of the final delay circuit 85 rises high immediately.
The NAND circuit 84a receives the detection signal nol and the output signal s2 of the final delay circuit 85 and provides a NAND output signal as the active time-out signal tout to the row control circuit 44 via the inverter circuits 84b and 84c. 
As shown in FIG. 5, when the word line activating signal plez rises with the refresh command signal refz held at high level, the detection signal nol rises. The active time-out signal tout falls after a delay time t2 from the rise of the detection signal nol (rise of the word line activating signal plez). That is, the precharging operation is completed.
Thereafter, when the word line activating signal plez falls with the refresh command signal refz held at high level, the detection signal nol falls, and in response to the fall of the detection signal nol, the active time-out signal tout rises immediately.
A disadvantage of this system is that the circuit area is increased by both the delay circuits 71 of the regulator control circuit 50 and the delay circuits 85 of the active time-out circuit 80.
Further, since the regulator control circuit 50 and the active time-out circuit 80 are separate from each other, different supply voltages are provided to the delay circuits, which is attributable to the impedance of a power line of the sense amplifier consuming the largest amount of power. This may result in the delay times t1 and t2 fluctuating relative to each other or each delay time fluctuating independently.
It is a first object of the present invention to provide an internal supply voltage generating circuit of a semiconductor device having reduced power consumption in an active mode.
It is a second object of the present invention to provide a supply voltage generating circuit having reduced circuit area and power consumption.
In a first aspect of the present invention, a method for controlling an internal power supply voltage generating circuit, which supplies power to an internal circuit of a semiconductor device, is provided. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to the internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. Then, at least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pause of the active mode. The first voltage-drop regulator is activated when the active pause is cancelled.
In a second aspect of the present invention, a method for controlling an internal supply voltage generating circuit that supplies power to a sense amplifier system internal circuit including a sense amplifier in a semiconductor memory device is disclosed. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to the sense amplifier system internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the sense amplifier system internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. At least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pause of the active mode. The first voltage-drop regulator is activated when the active pause is cancelled.
In a third aspect of the present invention, an internal supply voltage generating circuit of a semiconductor memory device is provided that supplies a driving power to a sense amplifier system internal circuit including a sense amplifier. The internal supply voltage generating circuit includes first and second voltage-drop regulators. The first voltage-drop regulator is connected to the sense amplifier system internal circuit. The first voltage-drop regulator is selectively activated in accordance with a first timing signal and supplies a relatively large driving power to the sense amplifier system internal circuit. The first voltage-drop regulator is activated when the semiconductor memory device shifts from one of a stand-by mode and a power-down mode to an active mode, is inactivated when the semiconductor memory device enters a state of an active pause in the active mode, and is activated when the active pause is cancelled. The second voltage-drop regulator is connected to the sense amplifier system internal circuit. The second voltage-drop regulator is constantly activated and supplies a relatively small driving power to the sense amplifier system internal circuit.
In a fourth aspect of the present invention, a control circuit for a supply voltage generating circuit, which supplies an internal supply voltage to an internal circuit, is provided. The internal circuit is selectively activated for a predetermined period in accordance with a control signal. The control circuit includes a signal generating circuit that generates a signal for controlling the control signal. The signal generating circuit includes an activating signal generating circuit that generates an activating signal for selectively activating the supply voltage generating circuit.
In a fifth aspect of the present invention, a semiconductor memory device is provided. The memory device includes a memory cell array and a row system circuit that controls the memory cell array. The row system circuit is selectively activated for a predetermined period of time in accordance with a first control signal. A supply voltage generating circuit supplies an internal supply voltage to the row system circuit in response to an activating signal. A signal generating circuit generates a second control signal for controlling the first control signal. The signal generating circuit includes an activating signal generating circuit that generates an activating signal for selectively activating the supply voltage generating circuit.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.